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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16661A
160-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH RAM
The PD16661A is a column (segment) driver containing a RAM capable of full-dot LCD drive. With 160 outputs, this driver has an on-chip display RAM of 160 x 240 x 2 bits. The driver can be combined with the PD16666A to display from 1/8 VGA to VGA (640 x 480 dots). The PD16661A is upwardly compatible with the PD16661.
FEATURES
* Display RAM incorporated : 160 x 240 x 2 bits * Logic voltage : 3.0 to 3.6 V * Duty : 1/240 * Output count : 160 outputs * Capable of gray scale display : 4 gray scales (frame thinning-out) * Memory management : packed pixel system * 8/16-bit data bus
ORDERING INFORMATION
Part Number Package TCP (TAB)
PD16661AN-xxx
5
PD16661AN-051
Standard TCP (OLB : 0.2 mm-pitch, pliable-output leads)
Remark The TCP package is custom made, so contact an NEC sales representative with your requirements.
The information in this document is subject to change without notice.
Document No. S11498EJ3V0DS00 (3rd edition) Date Published November 1998 NS CP (K) Printed in Japan
The mark 5 shows major revised points.
(c) NEC Corporation 1996,1998
PD16661A
PIN NAMES
Classification CPU interface Pin Name D0 to D15 A0 to A16 /CS 3.3 V /OE /WE /UBE RDY Control signals PL0 PL1 PL2 DIR MS BMODE GMODE 3.3 V /REFRH TEST /RESET /DOFF OSC1 OSC2 STB /FRM 5.0 V L1 L2 /DOUT Liquid-crystal drive Power supplies Y1 to Y160 GND VCC1 VCC2 V0 V1 V2 I/O I I I - - I/O I/O I/O I/O O O - - - - - -
Note
I/O I/O I I I I I O I I I I I I I
Pad No. Data bus : 16 bits Address bus : 17 bits Chip select Read signal Write signal Upper byte enable
Function
Ready signal to CPU (Ready state at "H") Specifies the LSI placement positions (No. 0 to 7) Specifies the LSI placement positions (No. 0 to 7) Specifies the LSI placement positions (No. 0 to 7) Specifies the liquid-crystal panel placement direction Master/slave selection pin (Master mode at "H") Data bus bit selection pin ("H" = 8 bits, "L" = 16 bits) Gray scale data weight reverse switching (When data = [1,1], "L" = black, "H" = white) Self-diagnosis reset pin (wired-OR connection) Test pin ("H" = test mode, on-chip pull-down resistor) Reset signal Display OFF input signal Oscillator externally-attached resistor pin Oscillator externally-attached resistor pin Column drive signal (MS pin "H" = output, MS pin "L" = input) Frame signal (MS pin "H" = output, MS pin "L" = input) Row driver drive level selection signal (1st line) Row driver drive level selection signal (2nd line) Display OFF output signal Liquid-crystal drive output Ground (two pins for VCC1 system , three pins for VCC2 system) 5-V power supply 3.3-V power supply Liquid-crystal drive analog power supply Liquid-crystal drive analog power supply Liquid-crystal drive analog power supply
Note 3.3-V pin : D0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, BMODE, GMODE, PL0, PL1, PL2, DIR, OSC1, OSC2, /RESET, /DOFF, TEST, MS 5-V pin : STB, /FRM, L1, L2, /DOUT 5 Remark /xxx indicates active low signal.
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PD16661A
BLOCK DIAGRAM
DIR PL0,1,2 TEST
Address input control Address management circuit
A0 to A16 Control /CS,/OE, /WE,/UBE RDY BMODE D0 to D15 GMODE /REFRH /RESET MS
Arbiter
RAM 160x240x2 bits
Data bus control
Data latch(1)
STOP OSC1 CR
oscillator
Frame thinning-out
FRC control
OSC2 /DOFF
Internal timing generation Data latch(2)
Liquid-crystal timing generation
3.3 V operation
/FRM STB
Self-diagnosis circuit
3.3 V operation
Level shifter 5.0V operation DEC 5.0 V operation
Liquid-crystal drive circuit 160 outputs
V0 V1 V2
/FRM
STB /DOUT L1
L2
Y1 Y2 Y3
Y160
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PD16661A
1. BLOCK FUNCTIONS
(1) Address management circuit The address management circuit converts the addresses transferred from the system via A0 to A16 into addresses compatible with the memory map of the on-chip RAM. This function can be used to address up to VGA size (480 x 640 dots) with 8 of these LSIs, thus making it possible to configure a liquid-crystal display system without difficulty.
(2) Arbiter The arbiter adjusts the contention between the RAM access from the system and the RAM read on the liquidcrystal drive side.
(3) RAM Static RAM (single port) of 160 x 240 x 2 bits
(4) Data bus control The data bus controls the data transfer directions by means of Read/Write from the system. The mode can be switched from 8 bits to 16 bits by the BMODE pin, and the relation between the display data and the gray scale can be switched by the GMODE pin.
(5) Frame thinning-out control The frame thinning-out control indicates the four gray scales with three thinning-out frames. The thinning-out method can be changed in units of 9 pixels (3 columns x 3 lines).
(6) Internal timing generation The internal timing to each block is generated from the /FRM and STB signals.
(7) CR oscillator In master mode, this oscillator generates the clock that is the reference for the frame frequency. The frame frequency is one 484th (1/484) of this oscillation. For example, if the frame frequency is 80 Hz, an oscillation frequency of 38.72 kHz is necessary. As the CR has a built-in capacitance, adjust the required oscillation frequency with an externally attached resistor. In slave mode, oscillation is stopped.
(8) Liquid-crystal timing generation In master mode, /FRM (the frame signal) and STB (the column drive signal strobe) are generated.
(9) FRC control This circuit realizes the four gray-scale displays.
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PD16661A
(10) Data latch (1) This data latch reads and latches 160-pixel data from the RAM.
(11) Data latch (2) This data latch synchronizes with the STB signal and latches 160-pixel data.
(12) Level shifter The level shifter converts the voltage from the operating voltage of the internal circuit (3.3 V) to the voltage of the liquid-crystal drive circuit and row driver interface (5.0 V).
(13) DEC The DEC decodes the gray scale display data to make it compatible with the liquid-crystal drive voltages V0, V1, and V2.
(14) Liquid-crystal drive circuit This circuit selects one of the display OFF signal (/DOFF)-compatible liquid-crystal drive power supplies V0, V1, or V2, and generates the liquid-crystal applied voltage.
(15) Self-diagnosis circuit This circuit automatically detects any occurrence of an operation timing lag between the master chip and the slave chip that has been caused by outside noise, and sends a refresh signal to all the column drivers.
2. MEMORY MAP
Address A16 0 0 0 : : 0 F 0 : : 1 D F : 1 F F F F H A 0 H Unused 0 0 H Display data of Nos. 1, 3, 5, and 7 0 0 A0 H Display data of Nos. 0, 2, 4, and 6
Description
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PD16661A
Address map image diagram (Example of VGA-size configuration)
Column direction specified with A7 to A0 Y1 Y160 Line direction specified with A16 to A8 L1 Address setting direction Y1 Y160 Y1 Y160 Y1 Y160
L240 L1
No.0
No.2
No.4
No.6
Address setting direction
L240
No.1 Y1 Y160
No.3 Y1 Y160
No.5 Y1 Y160
No.7 Y1 Y160
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PD16661A
3. DATA BUSES
The method for lining up byte data on the data bus line is essentially the Little Endian system adopted by NEC and Intel Corp.
3.1 16-bit data bus (BMODE = L) Byte unit access
D0 to D7 D8 to D15 00001H 00003H 00005H : :
The address setting direction is as shown on the right.
00000H 00002H 00004H : :
Word unit access
D0 to D7 D8 to D15 00000H 00002H 00004H : :
The address setting direction is as shown on the right.
For access from the system to be performed in word units (16 bits), or byte units (8 bits), /UBE (upper-byte enable) and A0 are used to show whether valid data is in the bytes of either (or both) D0 to D7 or D8 to D15.
I/O /CS H L /OE X L /WE X H /UBE X L L H L L H X H A0 X L H L L H L X H MODE D0 to D7 Not selected Read Hi-z Dout Hi-z Dout Din X Din Hi-z Hi-z D8 to D15 Hi-z Dout Dout Hi-z Din Din X Hi-z Hi-z
L
H
L
Write
L L
H X
H X
Output disable
Remark X : Don't care, Hi-z : High impedance
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PD16661A
3.2 8-bit data bus (BMODE = H)
D0 to D7
The address setting direction is as shown on the right.
00000H 00001H 00002H : :
I/O /CS H L L L /OE X L H H /WE X H L H Not selected Read Write Output disable MODE D0 to D7 Hi-z Dout Din Hi-z D8 to D15 Note Note Note Note
Note When BMODE = H, D8 to D15 and /UBE are pulled down internally, so either leave them open, or connect them to the GND.
Remark X : Don't care, Hi-z : High impedance
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PD16661A
4. RELATIONSHIP BETWEEN DATA BITS AND PIXELS
Because the display is in four gray scales, each pixel consists of two bits. The RAM is configured with four pixels (8 pixels per word) using the packed pixel system. (1) BMODE = L In byte unit access (8 bits)
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Pixel 6 Pixel 7 Pixel 8
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 5

00000H 00001H Liquid-Crystal Panel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
In word unit access (16 bits)
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Pixel 6 Pixel 7 Pixel 8

00000H Pixel 1 Pixel 2 Liquid-Crystal Panel
Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
00000H

00001H Pixel 3 Pixel 4
00000H

00002H Pixel 5

00003H

00002H
(2) BMODE = H
D0 D1 Pixel 1 D2 D3 Pixel 2 D4 D5 Pixel 3 D6 D7 D0 D1 D2 D3 Pixel 6 D4 D5 Pixel 7 D6 D7
Pixel 4
Pixel 5
Pixel 8

00000H 00001H Liquid-Crystal Panel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

00000H

00001H

00002H

00003H
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PD16661A
5. RELATIONSHIP BETWEEN DISPLAY DATA AND GRAY-SCALE LEVEL
(1) GMODE = L
Gray Scale Dn Dn+1 Level 0 1 0 1 0 0 1 1 0 1 2 3 ON OFF Display OFF State Display State Liquid-Crystal State
(2) GMODE = H
Gray Scale Dn Dn+1 Level 1 0 1 0 1 1 0 0 3 2 1 0 ON OFF Display OFF State Display State Liquid-Crystal State
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PD16661A
6. LSI PLACEMENT AND ADDRESS MANAGEMENT
Addresses can be managed to allow the use of a maximum of eight PD16661A devices for configuring a liquidcrystal display of up to VGA size (480 x 640 dots). Up to eight of these LSIs can be connected to the same data bus and to the /CS, /WE, and /OE pins, which are shared. One screen of the liquid-crystal display can be treated as one memory area in the system, so it is not necessary to decode more than one PD16661A device. The PL0, PL1, and PL2 pins are used to specify the LSI No. and determine the LSI placement. The DIR pin is used to determine the direction (perpendicular, lateral) of the liquid-crystal display.
PL2 0 0 0 0 1 1 1 1
PL1 0 0 1 1 0 0 1 1
PL0 0 1 0 1 0 1 0 1
LSI No. No. 0 No. 1 No. 2 No. 3 No. 4 No. 5 No. 6 No. 7
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PD16661A
Landscape VGA size address DIR = "0"
Specified with A7 to A0
Y8 Y1 L1 L2 00000 00100 No.0
Specified with A16 to A8
Y160 Y153 00026 00126 Y1
Y8
Y160 Y153 Y1
Y8
Y160 Y153 00076 00176 No.4 Y1
Y8
Y160 Y153 0009E 0019E No.6
00028 00128 No.2
0004E 00050 0014E 00150
00078 00178
L239 0EE00 L240 L1 L2 0EF00 0F000 0F100 No.1 L239 1DE00 L240 1DF00 Y153 Y160
0EE26 0EE28 0EF26 0EF28 0F026 0F126 0F028 0F128 No.3 1DE26 1DE28 1DF26 1DF28 Y1 Y8 Y153 Y160
0EE4E 0EE50 0EF4E 0EF50 0F04E 0F050 0F14E 0F150 No.5 1DE4E 1DE50 1DF4E 1DF50 Y1 Y8 Y153 Y160
0EE76 0EE78 0EF76 0EF78 0F076 0F176 0F078 0F178 No.7 1DE76 1DE78 1DF76 1DF78 Y1 Y8 Y153 Y160
0EE9E 0EF9E 0F09E 0F19E
1DE9E 1DF9E Y1 Y8
12
Specified with A7 to A0
Y8 Y160 Y160 Y153 00050 0004E 00150 0014E 00128 00126 00028 00026 00000 00100 Y1 Y153 Y1 Y153 L1 L2 Y160 Y153 00078 00178 00176 00076 Y1 Y8 Y160 Y1 0009E 0019E
Portrait VGA size address
Y8 Y8
DIR = "1"
Specified with A16 to A8
No.6
No.4
No.2
No.0
0EE9E 0EF9E 0F09E 0F19E 0F178 0F176 0F150 0F14E 0F078 0F076 0F050 0F04E 0EF78 0EF76 0EF50 0EF4E
0EE78 0EE76
0EE50 0EE4E
0EE28 0EF26 0EF28 0EF26 0F028 0F026 0F128 0F126
0EE00 0EF00 0F000 0F100
L239 L240 L1 L2
No.7
No.5
No.3
No.1
1DE9E 1DF9E Y153 Y160 Y8
1DE78 1DE76 1DF78 1DF76 Y1 Y153 Y160
1DE50 1DE4E 1DF50 1DF4E Y1 Y8 Y153 Y160
1DE28 1DE26 1DF28 1DF26 Y1 Y8 Y153 Y160
1DE00 1DF00 Y1 Y8
L239
PD16661A
L240
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PD16661A
7. CPU INTERFACE
7.1 Function of the RDY (Ready) pin The on-chip RAM uses a single-port RAM. In order to avoid conflict between accessing from the CPU side and reading on the liquid-crystal drive side, the RDY pin performs a wait operation on the CPU. 5 (1) Timing
A0 to A16,/UBE
/CS
/OE,/WE Hi-z RDY Hi-z
Wait
Ready
Wait
(2) Connection of the RDY pin The RDY pin uses a 3-state buffer. Externally attach a pull-up resistor to the RDY pin. When more than one PD16661A is used, wired-OR connect each LSI RDY pin.
VCC2 CPU Ready input
Pull-up resistor RDY Column driver
RDY
Column driver
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PD16661A
5 7.2 Access timing (1) Display data read timing
A16 to A0
/UBE
/CS
/OE Hi-z RDY Hi-z D15 to D0 Dout Hi-z Hi-z
(2) Display data write timing
A16 to A0
/UBE
/CS
/WE Hi-z RDY Hi-z
D15 to D0
Din
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PD16661A
8. GRAY SCALE CONTROL
The four gray scales are expressed in terms of 3 thinning-out frames. The thinning-out method is changed by 9 pixels: pixel numbers 1, 2, and 3, and line numbers 1, 2, and 3 of the liquid-crystal panel. Frame thinning-out method
Frame 1 1 1 Gray Scale 0 2 3 1 Gray Scale 1 2 3 1 Gray Scale 2 2 3 1 Gray Scale 3 2 3 Line 2 3 Frame 2 1 2 3 Frame 3 1 2 3 Column
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PD16661A
9. LIQUID-CRYSTAL TIMING GENERATION
9.1 Reset state In the reset state, the internal counter is zero-cleared. After the reset is released, the display OFF function operates during the 4-frame cycle, even if the /DOFF pin is at H.
/RESET 1 /FRM 2 3 4 5 6
/DOUT
Internal state Display OFF Display ON
9.2 Liquid-crystal timing generation circuit When the master mode is set with MS = H, this circuit generates the signals /FRM and STB at a duty ratio timing of 1/240. It also generates L1 and L2, which are the drive voltage selection signals for the row driver. The /FRM signal is generated twice per frame. The STB signal is generated 121 times per half frame, or 242 times per frame. Generation of /FRM & STB signals
OSC1
/FRM
STB 121 1 2 121 1 2 121 1 2
Frame
Generation of L1 and L2 signals
STB L1 L2
1 2 3 4 1 1 1 1 1 0 1 0
1 2 3 4 1 1 1 1 0 1 0 1
1 2 3 4 0 0 0 0 0 1 0 1
1 2 3 4 0 0 0 0 1 0 1 0
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PD16661A
10. SELF-DIAGNOSIS FUNCTION
This is a function to check whether or not there has been a delay in the operation timing of each column driver caused by external noise, etc. The slave chip compares the L1 and L2 signals of the master chip with the L1 and L2 signals generated internally, and if a mismatch is discovered, the slave chip sends a refresh signal to all the column drivers. When the refresh signal is received, the internal reset is activated, and the timing is initialized. At this time, the display turns OFF while /REFRH = L and during the four frame cycle. The L1 and L2 signals are checked for mismatch at the rising edge of /FRM once every half frame.
L1(Master) Mismatch L2 (Master) L1 (Slave) L2 (Slave) Mismatch
/REFRH Initialized Initialized
Block configuration diagram (Slave side)
/RESET
Internal reset
/REFRH Self-diagnosis circuit
L1 L2
Internal L1 signal Internal L2 signal
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PD16661A
11. SYSTEM CONFIGURATION EXAMPLE
This is an example of the configuration of a liquid-crystal panel of half VGA size (480 x 320, perpendicular) using four PD16661A devices and two row drivers. * Each column driver sets the LSI No. with the PL0, PL1, and PL2 pins. * The DIR pin of each column driver is set to low. * One of the column drivers only is set to master; all the others are set to slave. Signals are supplied from the master column driver to the slave column drivers and the row drivers. * The OSC1 and OSC2 pins have an oscillator resistor attached on the master, and are left open on the slaves. * All the signals from the system side (D0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, /RESET, /DOFF) are connected in parallel to the column driver. A pull-up resistor is attached to the RDY signal. * The TEST pin is used to test the LSI, and is left open or connected to the GND when the system is configured.
VCC2
STB /FRM /DOUT,/DOFF' L1 L2 /REFRH Y1 Row driver 240
OSC1
RDY /DOFF /RESET D0 to D15 A0 to A16 Control ( /CS, /OE, /WE, /UBE)
Master No.0
OSC2
Slave No.2
Y160 Y1 Scan direction
Y160
Scan direction Row driver 240
Y160
Y1 Y160
Y1
Slave No.1
Slave No.3
Remark /DOFF' is an input pin of row driver.
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PD16661A
5 12. CHIP SET POWER SUPPLY INPUT SEQUENCE It is recommended that the power supply be input in the following way. VCC2 VCC1 input VDD, VEE V1, V2 Make sure that the LCD drive voltages are input last.
ON VCC2 OFF ON 4.5 V
VCC1
OFF At least 0 s 0V
CPU Interface (A0 to A16, /CS, /OE, /WE, /UBE,D0 to D15, /DOFF) /RESET
Note1
3.3 V
3.3 V 0V At least 100 ns 0.3 VCC2 At least 0 s ON
VDD
Note2
OFF OFF
VEE
Note2
ON At least 0 s OFF ON ON
V1
V2
OFF
Notes 1. Inputting the selection pins (PL0, PL1, PL2, DIR, MS, BMODE) at the same time as the VCC2 pin is unproblematic. 2. It is not necessary to turn ON VDD and VEE at the same time. VDD and VEE are the liquid-crystal power supplies of the row driver.
Caution Disconnection of the chip set power supply is done in the reverse order of the input sequence.
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PD16661A
13. EXAMPLE OF THE CONFIGURATION OF THE MODULE - INTERNAL SCHOTTKY BARRIER DIODE FOR POWER SUPPLY PROTECTION REINFORCEMENT
VDD
Note
VCC1
V2
V1
V0
VSS
Note
VEE
Configure the diodes that are enclosed in the dotted lines when V0 is not 0 V (GND).
5
Note VDD and VEE are the liquid-crystal power supplies of the row driver.
Remark Use the Schottky Barrier Diode at Vf = 0.5 V or less.
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PD16661A
14. ELECTRICAL CHARACTERISTICS
Absolute maximum ratings (TA = +25 C)
Parameter Supply voltage (1) Supply voltage (2) Input /Output voltage (1) Input /Output voltage (2) Input/ Output voltage (3) Symbol VCC1 VCC2 VI/O1 VI/O2 VI/O3 Ratings -0.5 to +6.5 -0.5 to +4.5 -0.5 to VCC1 + 0.5 -0.5 to VCC2 + 0.5 -0.5 to VCC1 + 0.5 -20 to +70 -40 to +125 Unit V V V V V C C Remark
Note1 Note2 Note1 Note2 Note3, Note4
Operating ambient temperature Storage temperature
TA Tstg
Notes1. 5-V signals (/FRM, STB, /DOUT, L1, L2) 2. 3.3-V signals (MS, DIR, PL0 to PL2, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, OSC1, OSC2, /DOFF, TEST, GMODE, BMODE, /REFRH) 3. Liquid-crystal drive power supplies (V0, V1, V2, Y1 to Y160) 4. Set V0 < V1 < V2
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended operating range (TA = -20 to +70 C, V0 = 0 V)
Parameter Supply voltage (1) Supply voltage (2) Input voltage (1) Input voltage (2) V1 input voltage V2 input voltage OSC external resistor Symbol VCC1 VCC2 VI1 VI2 V1 V2 ROSC MIN. 4.5 3.0 0 0 V0 V1 300 TYP. 5.0 3.3 MAX. 5.5 3.6 VCC1 VCC2 V2 VCC1 700 Unit V V V V V V k Remark
Note1 Note2
Notes1. 5-V signals (/FRM, STB) 2. 3.3-V signals (MS, DIR, PL0 to PL2, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 toD15, /RESET, OSC1, OSC2, /DOFF, TEST, GMODE, BMODE, /REFRH)
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PD16661A
DC Characteristics (Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = -20 to +70 C)
Parameter High-level input voltage (1) VCC1 Low-level input voltage (1) VCC1 High-level input voltage (2) VCC2 Low-level input voltage (2) VCC2 High-level input voltage (2) VCC2 Low-level input voltage (2) VCC2 High-level output voltage (1) VCC1 Low-level output voltage (1) VCC1 High-level output voltage (2) VCC1 Low-level output voltage (2) VCC1 High-level output voltage (3) VCC2 Low-level output voltage (3) VCC2 Input leakage current (1) Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 II1 VCC2 - 0.4 0.4 10 VCC1 - 0.4 0.4 VCC1 - 0.4 0.4 0.8 VCC2 0.2 VCC2 0.7 VCC2 0.3 VCC2 MIN. 0.7 VCC1 0.3 VCC1 TYP. MAX. Unit V V V V V V V V V V V V Remark Note1 Note1 Note2 Note2 Note4 Note4 IOH = -1 mA, Note3 IOL = 2 mA, Note3 IOH = -2 mA, Note1 IOL = 4 mA, Note1 IOH = -1 mA, Note4 IOL = 2 mA, Note4 Other than TEST pin, VI = VCC2 or GND Pull-down (TEST pin), VI = VCC2 Master, VCC1, Note5 Master, VCC2, Note5 Slave, VCC1, Note5 Current consumption for display operation (4) Liquid-crystal driving output ON resistance ISLV2 RON 1 100 2 Slave, VCC2, Note5 k Note6
A
Input leakage current (2)
II2
10
40
100
A
Current consumption for display operation (1) Current consumption for display operation (2) Current consumption for display operation (3)
IMAS1 IMAS2 ISLV1
40 150 30
A A A A
Notes 1. 5-V signals (/FRM, STB,L1,L2) 2. 3.3-V signals (MS, DIR, PL0 to PL2, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, /DOFF, TEST, GMODE, BMODE) 3. /DOUT pin 4. D0 to D15, RDY, and OSC2 pins 5. When the frame frequency is 70 Hz, and the output and CPU are without load and access respectively. (D0 to D15, A0 to A16, and /UBE = GND, and /CS, /OE, and /WE = VCC2) 6. This is the resistance value between a Y pin and a V pin (V0, V1, or V2) when the load current (ION = 100 A) is passed to a pin of Y1 to Y160.
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PD16661A
AC Characteristics 1 Display data transfer timing Master mode (Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = -20 to +70 C, Frame frequency : 70 Hz (fOSC = 33.88 kHz), Output load : 100 pF)
Parameter STB Clock cycle time STB High-level width STB Low-level width STB Rise time STB Fall time STB - /FRM Delay time /FRM - STB Delay time Symbol tCYC tCWH tCWL tR tF tPSF tPFS 12 12 MIN. 58 28 28 TYP. 2/fOSC 1/fOSC 1/fOSC 100 100 MAX. Unit Remark
s s s
ns ns
s s
tCYC tCWL tF tCWH tR
STB (Output) tPSF tPFS tPSF tPFS 0.9 VCC1 /FRM (Output) 0.1 VCC1
0.9 VCC1 0.1 VCC1
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PD16661A
Slave mode (Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = -20 to +70 C)
Parameter STB Clock cycle time STB High-level width STB Low-level width STB Rise time STB Fall time /FRM Setup time /FRM Hold time Symbol tCYC tCWH tCWL tR tF tSFR tHFR 1 1 MIN. 10 4 4 150 150 TYP. MAX. Unit Remark
s s s
ns ns
s s
tCYC tCWL tF tCWH tR
STB (Input) tSFR tHFR tSFR tHFR 0.7 VCC1 /FRM (Input) 0.3 VCC1
0.7 VCC1 0.3 VCC1
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PD16661A
Master/Slave common items (Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = -20 to +70 C)
Parameter Output delay time (L1, L2, /DOUT) Output delay time (Y1 to Y160) Symbol tDOUT1 tDOUT2 MIN. TYP. 50 90 MAX. 100 150 Unit ns ns Remark Output without load Output without load
STB (Output)
0.9 VCC1
tDOUT1 L1, L2, /DOUT tDOUT2 0.9 V2
tDOUT1 0.9 VCC1
tDOUT2
0.1 V2 Y1 to Y160 0.9 V2 0.1 V2
26
PD16661A
AC Characteristics 2 Graphic access timing (Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = -20 to +70 C, tr = tf = 5 ns, frame frequency : 70 Hz (fOSC = 33.88 kHz))
Parameter /OE,/WE Recovery time Address setup time Address hold time RDY Output delay time Symbol tRY tAS tAH tRYR tRYZ tRYW tRYF1 tRYF2 tACS tHZ tCSOE tOECS tWP tDW tDH tCSWE tWECS tWRES tRDOE tRDWE 10 20 50 20 20 10 20 100 Note4 Note4 60 650 MIN. 30 10 20 30 30 35 100 1200 100 40 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -- -- Note1 CL = 15 pF Note3 Note1 Note1 Note1 Note2 Note3 Remark
5 5
RDY Float time Wait state time Ready state time (Without Contention) Ready state time (With Contention) Data access time (Read cycle) Data float time (Read cycle) /CS-/OE Time (Read cycle) /OE-/CS Time (Read cycle) Write pulse width (Write cycle) Data setup time (Write cycle) Data hold time (Write cycle) /CS-/WE Time (Write cycle) /WE-/CS Time (Write cycle) Reset pulse width RDY-/OE Time RDY-/WE Time
Notes 1. Load circuit
VCC2 1.8 k
1.0 k
60 pF
2.
Load circuit
VCC2 1.8 k
1.0 k
100 pF
27
PD16661A
5
3. Load circuit
VCC2 1.8 k
1.0 k
5 pF
4. The display may be affected if there is a long time from the rise of RDY to the /OE or /WE signals. It is recommended that tRDOE and tRDWE are 1000 ns or less.
28
PD16661A
/OE,/WE Recovery time
tRY 0.7 VCC2 /OE,/WE 0.3 VCC2
5
Read cycle
A16 to A0 /UBE tAS tAH
0.7 VCC2 0.3 VCC2
/CS
0.3 VCC2 tCSOE tRDOE tOECS 0.7 VCC2 0.3 VCC2 tRYR tRYF 0.1 VCC2 Hi-z tACS tHZ 0.1 VCC2 0.9 VCC2 0.1 VCC2 tRYW tRYZ
/OE
RDY
D15 to D0
Output
29
PD16661A
5 Write cycle
A16 to A0 /UBE tAS tAH
0.7 VCC2 0.3 VCC2
/CS
0.3 VCC2
tCSWE /WE tRYR RDY Hi-z 0.1 VCC2 tRYF
tRDWE
tWECS 0.7 VCC2 0.3 VCC2 tRYW tRYZ
tWP
0.1 VCC2
D15 to D0
Input
0.7 VCC2 0.3 VCC2
tDW
tDH
5 Reset pulse width
/RESET tWRES
0.3 VCC2
30
PD16661A
AC Characteristics 3 CR Oscillator (VCC2 = 3.0 to 3.6 V, TA = -20 to +70 C)
Parameter Oscillation Frequency Frame Frequency Symbol fOSC MIN. 32 66.1 TYP. 36 74.4 MAX. 40 82.6 Unit kHz Hz Remark External resistor 350 k External resistor 350 k
15. RELATIONSHIP BETWEEN THE OSCILLATION , FRAME , AND STB FREQUENCIES
This relationship is as follows: Frame frequency = 1 x Oscillation frequency 242 x 2
STB frequency =
1 x Oscillation frequency 2
31
PD16661A
44.860.08 18.5 18.5 (36) (Cut Line) 17.50.3 (SR) 17.50.3 (SR) 35 (Slit) 17 (Mark) P0.20.01x165 = 330.05 W0.10.015 17 (Mark)
1.420.03
20.01
4.750.03
2.375 1.2 (1.5) 4.20.2(SR) 1.075 5.625 0.8 10.2 (2.3) (12.5) (Cut Line) 13 13.8 14.5
0.20.2
13.8 10.2 Flex resin
0.12
(0.4)
P0.0808
(coating area)
P0.0815
1 D16661AN -051
JAPAN
6.8 -4.6
1 Cu
2.2
0
2.60.2 4
P0.1034
P0.1021
0.20.2
(0.5)
Standard TCP package drawing (PD16661AN-051)
16.57 100.3 (SR) 100.3 (SR) 13 (Hole) 13 (Hole) P0.450.01x73 = 32.850.045 W0.2250.02 170.3 (SR) 170.3 (SR) 35 20.2
(6.3) (Cut Line) 6.8
(1)
2
5 16. PACKAGE DRAWING
(coating area) 0 21.2 -4.6
This product is face up type. This product is singleflex resin type. This flgure is shown by Copper side over Polyimide. Detail see another sheet. 5 Sprocket holes (23.75 mm) for 1 Pattern. Corner radius is 0.30 mm Max. All tolerances unless otherwise specified 0.05 mm.
Specification Basefilm : UPILEX-S 75 m Adhesive : EPOXY 12 m COPPER FOIL : ELECTROLYSIS Cu 25 m Plating : Sn MIN. 0.25 m Solder Resist : EPOXY 25 m FLEX RESIN : POLYIMIDE COATING RESIN : EPOXY
SR
MAX. 0.9
Flex resin (1)
Polyimide
Copper
32
JAPAN
D16661AN-051
1
PD16661A
Test pad and alignment mark details (x20)
Alignment hole details (x20)
From P.C. From P.C. 20.01
18.5 17 P0.2 R0.6 PI Hole
0.2 R0.5 Cu Hole
0.60.015
0.40.015
0.3 0.4 0.4 0.3 0.2 0.3 0.2 0.3 0.2 (0.5) R0.8 Cu
0.06
1.2 PI Hole
1 Cu Hole
0.60.015
0.40.015
1.6 Cu
(12.5)
14.5
13.8
10.2
From P.C.
0.10.015
TCP tape winding direction
Output lead
Tape pull-out direction Wind-up direction The Cu pattern side is the underside of the tape.
33
PD16661A
Standard TCP package drawing (PD16661AN-051)
Pin connection diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 NC V0 V1 V2 VCC1 GND VCC2 GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VCC2 OSC1 OSC2 GND DIR PL0 PL1 PL2 /REFRH /RESET /UBE /CS /OE /WE RDY /DOFF TEST BMODE GMODE MS VCC2 GND /FRM STB /DOUT L2 L1 VCC1 GND V2 V1 V0 NC NC NC NC Y160 Y159 Y158 Y157 Y156 Y155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Y5 Y4 Y3 Y2 Y1 NC NC NC 1 2 3 4 5 6 7 8 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 160 161 162 163 164 165 166
34
DIE FACE UP
PD16661A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
35
PD16661A
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

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